1. Technical Field
The device, system and method relates generally to electronic nanotechnology, and more specifically to Chemically Assembled Electronic Nanotechnology (CAEN) electronic devices and circuits.
2. Description of Related Art
In 1985, Keyes argued that the silicon transistor would not be easily replaced as the building block in digital circuits. See Robert W. Keyes, xe2x80x9cWhat Makes A Good Computer Device?xe2x80x9d Science, October, 1985, 230(4722), pp. 138-44. Although faster switching technologies have been introduced, none possess the wide array of desirable features to match silicon such as: current gain, voltage restoration, noise reduction, tolerance to variability in the manufacturing process, isolation of inputs from outputs, excellent fan-in and fan-out, the ability to invert a signal, tolerance to the high demands of a system environment, and a huge body of research and financial commitment to their use and manufacture. Since that time, advancements in Complementary Metal Oxide Semiconductor (CMOS) technology have increased speed and decreased the size of transistors at a phenomenal rate; recent work has produced 30-nm CMOS gates that switch in less than 2 ps. See R. Chau et al., xe2x80x9c30 nm Physical Gate Length CMOS Transistors With 1.0 ps N-MOS and 1.7 ps P-MOS Gate Delays,xe2x80x9d International Electron Devices Meeting, December, 2000.
Impressive as these results have been, in the near future further increases in the performance of silicon-based, lithographically manufactured transistors will be difficult to achieve. First, the small line widths necessary for next-generation lithography require the use of increasingly shorter wavelength light, which introduces a host of problems that are currently being addressed. In addition, as the number of atoms constituting a device decreases, manufacturing variability of even a few atom widths can become significant and lead to defects.
More important, however, is the economic barrier to commercial nanometerscale lithography. New fabrication facilities costing orders of magnitude more than present ones will be required to produce chips with the required densities while maintaining acceptably low defect rates. The increasing cost of chip masks, which generally must be manufactured to single-atom tolerances, precludes commercially viable development of new chips except for the highest-volume integrated circuits (ICs). It is entirely possible that further reduction of transistor size will be halted by economic, rather than technological factors.
This economic downside is a direct consequence of lithographic fabrication because construction of devices and their assembly into circuits occurs at the same time. Keyes pointed out that the great advantage of silicon is that mass fabrication of transistors is extremely inexpensive on a per transistor basis. As Keyes also highlighted, however, this produces a set of constraints in that each element in the system must be highly reliable and devices cannot be tested, adjusted, or repaired after manufacture. These constraints force the design of the circuit to be tightly integrated with manufacture, because no additional complexity can be introduced into the circuit after its manufacture. Lithography is perfectly tuned to deal with these constraints, but at small scales the constraints become the obstacle to further improvements. To be widely accepted, any technology hoping to displace lithographically produced CMOS integrated circuits must overcome these obstacles, while sacrificing neither performance nor the low per-unit cost made possible by mass production.
Chemically assembled electronic nanotechnology (CAEN) holds promise as a technology to overcome these obstacles. It takes advantage of chemical synthesis techniques to construct circuit elements. Synthesis can occur in bulk, producing enormous quantities (moles) of identical devices, or devices can be grown in situ. Many different molecular scale devices have already been synthesized, including negative differential resistors (NDR) (See J. Chen, M. A. Reed, A. M. Rawlett and J. M. Tour, xe2x80x9cObservation Of A Large On-Off Ratio And Negative Differential Resistance In An Electronic Molecular Switch,xe2x80x9d Science, 1999, 286, pp. 1550-52; J. Chen and M. A. Reed, xe2x80x9cMolecular Wires, Switches And Memories,xe2x80x9d Molecular Electronics 2000, December, 2000), resistors, transistors, diodes, and reconfigurable switches (See J. Chen et al., xe2x80x9cRoom-Temperature Negative Differential Resistance In Nanoscale Molecular Junctions,xe2x80x9d Applied Physics Letters, 2000, 77(8), pp. 1224-26; C. P Collier, E. W. Wong, M. Belohradsky, F. M. Raymo, J. F. Stoddart, P. J. Kuekes, R. S. Williams and J. R. Heath, xe2x80x9cElectronically Configurable Molecular-Based Logic Gates,xe2x80x9d Science, July, 1999, 285, pp. 391-93). In all cases, the fabricated devices are on the order of a few nanometers and exploit the quantum mechanical properties of their constituents for proper operation.
While no direct comparison between CAEN and CMOS devices is possible, CAEN devices are relatively very small. A single CAEN switch-diode pair (as used in the circuits described hereinafter) will generally require an area of about 800 n2 as opposed to 100,000 nm2 for a single laid-out CMOS transistor. For example, a CAEN device can be implemented with nanowires on 20 m centers. In contrast, a CMOS transistor with a 4:1 ratio in a 70 nm process, (even using Silicon on Insulator, which does not require wells) with no wires attached measures 210 nmxc3x97280 nm. Attaching minimally sized wires to the terminals increases the size of the CMOS device to 350 nmxc3x97350 nm. A simple CMOS logic gate or static memory cell requires several transistors, separate p- and n-wells and wiring interconnects, resulting in a factor of more than one hundred difference in density between CAEN and CMOS. Furthermore, CAEN devices use a lot less power relative to CMOS devices because very few electrons are required for switching.
Alone, however, molecular-scale devices cannot overcome the limiting constraints of CMOS technology unless a suitable manufacturing technique can be devised for forming molecular-scale devices into circuits. Their small size and the fact that many are created separately from the circuit assembly process, means that it would be difficult to individually connect the nanoscale components. Economic viability requires that they be created and connected through self-assembly and self-alignment techniques. Several groups have recently demonstrated CAEN devices that are either self-assembled or self-aligned, or both. See C. P Collier, E. W. Wong, M. Belohradsky, F. M. Raymo, J. F. Stoddart, P. J. Kuekes, R. S. Williams and J. R. Heath, xe2x80x9cElectronically Configurable Molecular-Based Logic Gates,xe2x80x9d Science, July, 1999, 285, pp. 391-93; N. Spencer M. V. Martinez-Diaz and J. F. Stoddart, xe2x80x9cThe Self-Assembly Of A Switchable Rotaxane,xe2x80x9d Angewandte Chemie International Edition English, 1997, 36, p. 1904; A. Nakajima et al., xe2x80x9cRoom Temperature Operation Of Si Single-Electron Memory With Self-Aligned Floating Dot Gate, Appl. Phys. Lett, 1997, 70, pp. 1742, 1997; and T. Rueckes, K. Kim., E. Joselevich., G. J. Tseng, C. -L. Cheung and C. M. Lieber, xe2x80x9cCarbon Nanotube-Based Nonvolatile Random Access Memory For Molecular Computing,xe2x80x9d Science, 2000, 289, pp. 94-97. Advances also have been made in creating wires out of single-wall carbon nanotubes and aligning them on a silicon substrate. See S. J. Tans et al, xe2x80x9cIndividual Single-Wall Carbon Nanotubes As Quantum Wires,xe2x80x9d Nature, April, 1997, 386(6624), pp. 474-77; H. Park, A. K. L. Lim, J. Park, A. P. Alivisatos and P. L. McEuen, xe2x80x9cFabrication Of Metallic Electrodes With Nanometer Separation By Electromigration,xe2x80x9d www.physics.berkeley.edu/research/mceuen/topics/nanocrystal/EMPaper.pdf, 1999. Even more practically, metal nanowires, which scale down to 5 nm and include embedded devices, have been fabricated. See B. R. Martin, D. J. Dermody, B. D. Reiss, M. Fang, L. A. Lyon, M. J. Natan, and T. E. Mallouk, xe2x80x9cOrthogonal Self Assembly On Colloidal Gold-Platinum Nanorods,xe2x80x9d 1999, Advanced Materials, 11, pp. 1021-25; J. K. N. Mbindyo, B. D. Reiss, B. R. Martin, B. D. Reiss, M. J. Keating, M. J. Natan, and T. E. Mallouk, xe2x80x9cDNA-Directed Assembly Of Gold Nanowires On Complementary Surfaces,xe2x80x9d Advanced Materials, 2000.
Self-assembly of devices to form circuits imposes an entirely different set of constraints than lithography. Almost by definition, self-assembly will be an imprecise, thermodynamically controlled process. Therefore, one can no longer rely on the presence of highly reliable devices. Logically, this implies that the devices must be testable, adjustable, and/or repairable after manufacture to produce a working circuit, which also implies that some defects must be tolerated. Additionally, self-assembly can only produce a limited range of circuit complexity while remaining manageable. This requires a decoupling of the manufacturing process and the underlying architecture produced. Any deterministic aperiodic circuit will have to be created after the device is fabricated through a process known as reconfiguration.
One embodiment of the present invention provides a latch, including: a first resonant tunneling diode having a first end and a second end, the first end forming an input node; and a second resonant tunneling diode having a first end and a second end, wherein the second end of the first resonant tunneling diode is connected to the first end of the second resonant tunneling diode forming a data node at a connection point therebetween; wherein an input voltage can be applied to the data node for latching a logic state at the data node.
Another embodiment of the present invention provides a circuit, including: a first combinational circuit; a first latch connected to the first combinational circuit, wherein the first latch is driven by a first clock signal and the first combinational circuit is powered by a first voltage; a second combinational circuit connected to the first latch; and a second latch connected to the second combinational circuit, wherein the second latch is driven by a second clock signal and the second combinational circuit is powered by a second voltage; and a power supply clocking scheme to provide Input/Output isolation, wherein the first clock and the first voltage are applied to the first latch and the first combinational circuit and the second clock and the second voltage are applied to the second latch and the second combinational circuit to provide Input/Output isolation between first latch and the first and second combinational circuits and the second latch; and wherein each of the first and second latches further include: a first resonant tunneling diode having a first end and a second end, the first end forming an input node; a second resonant tunneling diode having a first end and a second end, wherein the second end of the first resonant tunneling diode is connected to the first end of the second resonant tunneling diode forming a data node at a connection point therebetween; and an isolation circuit connected to the data node.
Yet another embodiment of the present invention provides a circuit, including: a combinational logic circuit having an input and an output and power supply input; and a latch having an input and an output and a clock input, the latch input is connected to the output of the combinational logic circuit; wherein the latch is driven by a power supply clocking scheme for providing Input/Output isolation; and wherein when a clock signal is applied to the latch the combinational logic circuit power supply input is modified to enable the operation of the latch and provide the Input/Output isolation between the combinational logic circuit and the latch; and wherein the latch further includes: a first resonant tunneling diode having a first end and a second end, the first end forming an input node; a second resonant tunneling diode having a first end and a second end, wherein the second end of the first resonant tunneling diode is connected to the first end of the second resonant tunneling diode forming a data node at a connection point therebetween; and an isolation circuit connected to the data node of the latch.
A further embodiment of the present invention provides a circuit, including: a chemically assembled electronic nanoblock having an input and an output; wherein the nanoblock can be programmed to implement a logic function.
Yet another embodiment of the present invention provides a method for constructing a molecular integrated circuit using chemically assembled electronic nanotechnology, including: forming an array of electrical wires on a substrate via a chemical self-assembly process; aligning the array of electrical wires; combining the array of electrical wires and forming a two dimensional grid-like structure; and creating an active electronic device at an intersection point of two wires on the grid-like structure.
Still another embodiment of the present invention provides a method of fabricating a chemically assembled electronic nanotechnology molecular latch, including: forming a first resonant tunneling diode having a first and second end on a chemically assembled electronic nanotechnology grid-like structure forming a nanoblock; connecting a second resonant tunneling diode having a first and second end to the first resonant tunneling diode and forming a data node therebetween, wherein the second end of the first resonant tunneling diode is connected to the first end of the second resonant tunneling diode; and connecting an isolation circuit to the data node.
Still a further embodiment of the present invention provides a method of fabricating a chemically assembled electronic nanotechnology circuit, including: forming a chemically assembled electronic nanotechnology molecular nano-fabric; forming a plurality of clusters on the nano-fabric; forming a plurality of long lines and adjacently disposing the long lines to each of the clusters for communicating signals between the clusters; and forming a nanoblock in at least one of the clusters and connecting an in-line latch to the nanoblock.
These and various other features of the embodiments of the present invention will become apparent to those skilled in the art from the following description and corresponding drawings. As will be realized, the present invention is capable of modification without departing from the scope of the invention. Accordingly, the description and the drawings are to be regarded as being illustrative in nature, and not as being restrictive.